1. Technical Field
The disclosure relates to a wafer level molding structure and a manufacturing method thereof.
2. Related Art
It is one of the most promising solutions to resolve operations of a future large-scale chip to use a three-dimensional (3D) integrated circuit (IC) integration technology to provide a high-density chip packaging technique and achieve high efficiency and low power consumption. Particularly, in applications of data transmission between a flash memory and a controller of a central processing unit (CPU), a flash memory, or a memory card, a performance advantage of a short distance internal bonding path implemented by through-silicon-vias (TSV) is more obvious.
Therefore, in the portable electronic products emphasizing on multifunction and small size, for example, newly designed stacking structures of a solid state disk (SSD) and a dynamic random access memory (DRAM), etc, besides the high speed transmission is strengthened, power consumption of the chip is also reduced. In case of the same number of input/output pins, the required driving power is reduced, and demand for increasing the capacity, performance and I/O pins is synchronously resolved. Moreover, miniaturization of the 3D chip is a primary factor in market application, and main techniques of the 3D chip integration technology include TSV, micro bump contact fabrication, wafer thinning, alignment, bonding and adhesive dispensing.
Since a wafer-on-wafer (WOW) technique still has a problem of insufficient known-good dies (KGD), a whole packaging yield cannot be ameliorated. Therefore, a chip-to-chip (COC) bonding technique and a chip-to-wafer (COW) bonding technique are used to resolve the above problem, and how to assemble and stack the KGDs of a large amount based on the COC and COW bonding technique, confirm a contact yield and reduce the manufacturing cost are main consideration factors.
In a current 3D chip integration technique, the stacking technique is developed towards a pitch level of 10 micrometers (μm) and thin chips with a thickness level below 50 μm. In order to improve productivity and production yield, the bonding technique is gradually changed from the COC bonding technique to the COW packaging technique, and how to improve the bonding yield and reduce the manufacturing cost are still important issues.
FIG. 1 is a structure schematic diagram of the conventional COW packaging technique using an underfilling process. A wafer 120 is located on a carrier 100, and a cushion layer 110 is disposed there between. Each stacked chip structure 122 comprises three layers of chips 130, 140 and 150, which are electrically bonded with the wafer 120 through Cu bumps or Cu/SnAg micro bumps. Then, an underfill filing process and a molding process are performed to form an underfill layer 160 and a molding layer 170. Since the stacking technique is developed towards a pitch level of 10 micrometers (μm) and thin chips with a thickness level below 50 μm, after the underfill filling process, an overflow problem is occurred, which may influence a yield of the COW packing technique.
Since three steps of stacking, underfilling and molding have to be performed, relatively more time is spent on manufacturing processes, which may increase the manufacturing cost. Different materials are used in the underfilling process and the molding process, which may also increase the fabrication cost. Moreover, since the chip stacking structures are electrically connected through metal joints, the thermal expansion mismatch may also decrease the production yield.
FIG. 2 is a structure schematic diagram of the conventional COW packaging technique using a non-flow underfill (NFU) process. A wafer 220 is located on a carrier 200, and a cushion layer 210 is disposed there between. Each stacked chip structure 222 comprises three layers of chips 230, 240 and 250. The three layers of chips 230, 240 and 250 are respectively pre-adhered with NFUs 232, 242 and 252, and are electrically bonded with the wafer 220 through Cu bumps or Cu/SnAg micro bumps. Then, the molding process is performed to form the molding layer 270.
Since the NFU process has to be performed to adhere the NFU material on the chips, and then the steps of stacking and molding are performed, relatively more time is spent on manufacturing processes, which may increase the manufacturing cost. Different materials are used in the NFU adhering process and the molding process, which may also increase the manufacturing cost. Moreover, since the chip stacking structures are electrically connected through metal joints, the thermal expansion mismatch may also decrease the production yield.